The present invention relates to junction isolation of high voltage power integrated circuits and, more specifically, relates to improving heat dissipation in high voltage power integrated circuits by using a high (wide) band-gap material as an insulating layer.
Currently, most high voltage integrated circuits are designed and manufactured using junction isolation. Some of the problems that are associated with junction isolation include: (i) difficulty in integrating lateral bipolar devices without parasitic current flow in the substrate material; (ii) likelihood of "latch-up" in CMOS circuits when high dv/dt conditions are present, such as during high voltage switching; and (iii) relatively high leakage current flow in the junction materials at high ambient temperatures.
Dielectric isolation mitigates the above problems. However, the dielectric isolation introduces other problems, such as difficulty in providing heat dissipation through the dielectric isolation material as well as wafer-warpage due to the thick oxides needed to vertically support high-voltage.
Accordingly, a need exists in the electronic semiconductor device art for a structure which provides dielectric isolation that mitigates the problems encountered using junction isolation, which provides adequate heat dissipation of the semiconductor devices irrespective of the dielectric isolation material used and which is not susceptible to wafer-warpage.